Nonvolatile semiconductor memories use a variety of semiconductor memory cell designs. One type of memory cell uses an electrically isolated floating gate to trap charge. A variety of mechanisms can be used to insert charge into the floating gate and to pull charge from it. Electron tunneling can be used both to inject charge and to pull charge off the floating gate of a memory cell. Hot electron injection is another mechanism for inserting charge into a floating gate of a memory cell. Other nonvolatile semiconductor memories use a trapping dielectric to insert or remove charge from between the control gate of a memory cell and silicon.
An attractive feature of nonvolatile semiconductor memories is their ability to retain data when powered off. Another attractive feature of nonvolatile semiconductor memories is their ability to store analog data. This permits storage of multiple bits of data in a single memory cell, which is sometimes called multistate storage.
There are prior patents that discuss multistate storage. U.S. Pat. No. 5, 043,940 of Harrari for FLASH EEPROM MEMORY SYSTEMS HAVING MULTISTATE STORAGE CELLS ("Harrari") defines four states in terms of the threshold voltage V.sub.t of a split-channel memory cell. Using these four states, Harrari is able to store two bits of data per memory cell by applying multiple programming pulses to each memory cell.
U.S. Pat. No. 5,163,021 of Mehrota et al. for MULTI-STATE EEPROM READ AND WRITE CIRCUITS AND TECHNIQUES ("Mehrota") describes multilevel programming of split-channel memory cells in greater detail. Like Harrari, Mehrota defines four states in terms of memory cell threshold voltage. Mehrota describes programming multiple memory cells in parallel. A program pulse is applied to a group of cells simultaneously. Each cell is then program verified and those cells that are properly programmed are protected from further programming. Program pulses are applied until all memory cells in the group are properly programmed. Mehrota discloses using the same voltage levels for each subsequent programming pulse.